1. Field of the Invention
The present invention generally relates to a display and a display panel thereof, and more particularly, to a display with reduced crosstalk and a display panel thereof.
2. Description of Related Art
In recent years, many portable electronic products and flat panel display products have been developed along with the advancement of semiconductor technology. Among different types of flat panel displays, liquid crystal display (LCD) has become the mainstream of display products thanks to its many advantages, such as low-voltage operation, no scattering radiation, light weight, and small volume.
FIG. 1 is a diagram of a display panel of a conventional LCD. As shown in FIG. 1, each pixel P of the display panel 100 is coupled to a corresponding scan line 110 and a corresponding data line 120 through an active device (i.e., a thin film transistor (TFT)) TR, and only one data line 120 is disposed between every two pixel columns. In other words, the pixels in the same column share the same data line 120. Besides, the frame rate of the LCD illustrated in FIG. 1 is usually 60 Hz (i.e., the frame is updated 60 times during every second), wherein the greater the frame rate is, the higher image quality the LCD has.
In order to improve the display quality of dynamic images, LCDs with frame rates of 120 Hz and 240 Hz have been brought into the market. However, the charge time of each pixel P decreases along with the increase of the frame rate, wherein the charge time=(1/frame rate)/total number of scan lines. For example, assuming that the display panel 100 has a resolution of 1920*1080 (full HD) and is applied to an LCD with a frame rate of 120 Hz, the charge time of each pixel P is then 1/(120*1080)≈7 us. In this case, the charge time of each pixel P is still within an acceptable range. However, if the frame rate is increased, the charge time of each pixel P will be too short and thus causing that each of the pixels P is charged insufficiently.
To be specific, assuming that the display panel 100 also has a resolution of 1920*1080 but is applied to an LCD with a frame rate of 240 Hz, the charge time of each pixel P becomes 1/(240*1080)≈3.5 us. Because the charge time is too short, each pixel P cannot be charge to the appropriate voltage level and accordingly cannot display the correct grayscale (i.e., image distortion). As a result, the image quality of the LCD is reduced. Accordingly, a driving technique referred to as “half gate, two data (hG2D)” is developed.
Referring to FIG. 2, the display panel 200 is fabricated by adopting the hG2D driving technique, wherein two data lines 210 are disposed between every two pixel columns As shown in FIG. 2, in each pixel column, two adjacent pixels P are coupled to different data lines 210. Thus, two pixel rows are charged together during the same scan period. Namely, the charge time of each pixel P in the display panel 200 is twice that of each pixel P in the display panel 100.
For example, assuming that the display panel 200 has a resolution of 1920*1080 and is applied to an LCD with a frame rate of 240 Hz, the charge time of each pixel P is then 2*1/(240*1080)≈7 us. Accordingly, the problem of inadequate charge time of each pixel P produced when a full HD display panel is applied to an LCD with the frame rate of 240 Hz is resolved. However, this problem will be produced again if the frame rate is further increased or the resolution of the display panel is increased.
FIG. 3 and FIG. 4 are respectively diagrams of LCD panels disclosed in U.S. Pat. No. 6,809,719 and U.S. publication No. 20080068524. As described above, if the frame rate or resolution is higher than that of the display panel 200 (for example, the frame rate is 360 Hz or 480 Hz or the resolution is 4K2K (i.e., 3840*2160)), the charge time of each pixel P won't be adequate even though it is prolonged twice. Thus, the charge time of each pixel P is prolonged in the display panels 300 and 400 disclosed in the U.S. Pat. No. 6,809,719 and the U.S. publication No. 20080068524.
In the display panel 300, each pixel P includes a liquid crystal capacitor CL and a storage capacitor CS, and three data lines 310 are disposed between every two pixel columns. Thus, in each pixel column, every three adjacent pixels P are respectively coupled to different data lines 310 so that three pixel rows can be charged together during the same scan period. Accordingly, the charge time of each pixel P in the display panel 300 is three times of that of each pixel P in the display panel 100. In the display panel 400, four data lines 410 are disposed between every two pixel columns. Thus, in each pixel column, every four adjacent pixels P are respectively coupled to different data lines 410 so that four pixel rows can be charged together during the same scan period. Accordingly, the charge time of each pixel P in the display panel 400 is four times of that of each pixel P in the display panel 100.
As described above, the driving technique adopted by the display panel 300 may be considered as a 3-data driving technique, and the driving technique adopted by the display panel 400 may be considered as a 4-data driving technique. However, in foregoing display panels 300 and 400, some pixels P have to cross over other data lines 310 or 410 to be coupled to the corresponding data lines 310 or 410 (as the place A and the place B illustrated in FIG. 3 and FIG. 4). Herein, lines (i.e. data lines) crossing may result in unnecessary cross-over capacitances and accordingly the crosstalk may be produced to cause the local frame producing the color washout. In addition, a 4-sided driving technique has to be adopted if the pixels P are not to be coupled to the data lines 310 or 410 through lines crossing in the 3-data or 4-data driving technique. Namely, the control boards would be disposed respectively at the upper and lower side of the display panel. As a result, the cost of the display panel is increased.